Jyothish p j (Last Active: one year ago)

Design Engineer

Profile Status(Active)

************@*****.*** (Not Verified)

********** (Verified)

1 - 2 years Exp

2 - 3 lakhs Per Annum

Full Time

FPGA VLSI c verilog VHDL Orcad MATLAB

Summary

I have 2.5 years of experience as FPGA Design Engineer in a reputed product based company M/S. United Electronics. I design FPGA based board which is programmed with my HDL code. The FPGA device will be selected by checking the "Device Utilization Summary" (in Xilinx 13.1). Schematic will draw in "Orcad capture ". Assembled board will be tested by me.

Snapshot

Resume Headline: IT Software - Embedded /EDA /VLSI /ASIC /Chip Des., currently living in Bangalore/Bengaluru
Current Designation: Design Engineer
Current Company: united electronics
Current Location: Bangalore/Bengaluru
Preferred Location: Bangalore/Bengaluru
Industry: Semiconductors/Electronics
Functional Area: IT Software - Embedded /EDA /VLSI /ASIC /Chip Des.
Role: Software Developer
Date of Birth: September 2nd, 1988
Gender: Male
Key Skills: FPGA, VLSI, C, VERILOG, VHDL, ORCAD, MATLAB
Total Experience: 1 - 2 years Exp
Annual Salary: Rs. 2 lakh(s) 0 thousand(s)
Highest Degree: M.E/M.Tech
Phone: **********
Email: ************@*****.***
Permanent Address: ******, *********, *********, *****
Marital Status: Single/unmarried

Education

Masters Education

Post Graduation:M.E/M.Tech
Post Graduation Type: Full Time
Post Graduation Specialization:Electronics/Telecommunication
Post Graduation University/Institute:Vesveswaraiah Technological University, Belgaum
Post Graduation Year:October 2nd, 2012 To May 20th, 2014
Post Graduation CGPA / %:72

Bachelors Education

Graduation:B.E/B.Tech
Graduation Type: Full Time
Graduation Specialization:Electronics/Telecommunication
Graduation University/Institute:Cochin University of Science & Technology, Kochi
Graduation Year:September 24th, 2007 To May 17th, 2011
Graduation CGPA / %:6.2

Class 12th

Class 12th:PUC/12th
Class 12th Type: Full Time
Class 12th Specialization:Mathematics Physics Chemistry Biology
Class 12th University/Institute:State boards
Class 12th Year:September 1st, 2004 To April 11th, 2006
Class 12th CGPA / %:72

Class 10th

Class 10th:SSLC
Class 10th Type: Full Time
Class 10th Specialization:Malayalam
Class 10th University/Institute:State boards
Class 10th Year:June 1st, 1994 To April 12th, 2004
Class 10th CGPA / %:82

Skill Set

Skill Name Version Years Months
FPGA Not Mentioned 31
VLSI Not Mentioned 21
c Not Mentioned 21
verilog Not Mentioned 30
VHDL Not Mentioned 10
Orcad Not Mentioned 05
MATLAB Not Mentioned 10

Work Experience

Current Employer

Employer Name:united electronics
Employer Designation:Design Engineer
Annual Salary:2 Lakhs and 0 Thousands
Employer Notice:15 Days or less
Duration:September 16th, 2015 To Till Date
Employer Job Profile:Designing of FPGA based communication boards with user interfaces..

Additional information

Desired Job Information

Job Type:Permanent
Employment Type:Full Time

Affirmative Action

Categories:General
Physically Challenged:No

Work Authorization

Work Categories:None
Other Countries:N/A

Known Languages

Language Read Write Speak Proficiency
Malayalam Expert
English Proficient
Tamil Proficient
Kannada Beginner
Hindi Beginner

Contact Details

Name: Jyothish p j
Address: ******, *********, *********, *****
Email: ************@*****.***
Mobile: **********
Current Location: Bangalore/Bengaluru
Twitter: Not Mentioned
Facebook: Not Mentioned
Google Plus: Not Mentioned
LinkedIn: Not Mentioned
Skype: Not Mentioned